The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to a clustered architecture that is aware of variations.
Typically, a processor's clock frequency is set according to the critical path (worst-case) delay plus safety margins due to the magnitude of semiconductor manufacturing process (P), operating voltage (V), temperature (T), and input vectors or values (I) variations (PVTI). Generally, PVTI-related variations increase with technology scaling and, as a result, safety margins are becoming a more dominant component in determining a processor's clock.
Also, as the magnitude of PVTI variations grows, safety margins may have an increasing impact on a processor's performance. First, circuit verification may be more complex since variations may transform non-critical paths into critical path. Second, the clock frequency may have to be set to lower values to ensure correctness of processing results, which may have a cost implication. For example, low performance parts may need to be discarded which may increase costs.